Efficient implementation of composite length fast FIR filtering on the "ADSP-2100"

This paper proposes an efficient implementation of Fast Composite Length FIR algorithms on the Digital Signal Processor (DSP) "ADSP-2100", which closely follows the mathematical structure of the algorithm. The difficulty is to keep as much as possible the improvement brought by the reduction of the complexity without exceeding the DSP difficulty was already pointed out in previous papers, in which the algorithm was restricted to a single decomposition due to these constraints. A particular attention was devoted to this problem. The solution is to structurate the algorithm in such a way that the organization of data in memory is optimised. We propose an implementation requiring only five pointers whatever the number of iterations. An improvement of more than 50% in terms of actual throughput (number of cycles per point) compared to the implementation of the direct convolution is achieved. Finite Impulse Response (FIR) filtering is an important operation in Digital Signal Processing (DSP) applications which require a quite long impulse response (l i e matched filtering or acoustic echo cancellation). However, they require a great number of arithmetic operations. In order to reduce this number of arithmetic operations, various Fast FIR filtering algorithms were proposed. Some of them are based on cyclic or aperiodic convolution, while ones other use the Fast Fourier Transform (FFT) as an intermediate step. The fxst characteristic of these algorithms is that they process a large block of data (input), thus introducing a processing delay which may affect the application. Another problem is that they are not suitable for implementation on the recent generation of Digital Signal Processors (DSPs). The main architectural characteristic of these novel DSPs is that they integrate a fast Multiply-Accumulate (MAC), several independent memories and address generators performing a modulo addressing of circular buffers. The MAC allows to do one multiplication and one addition (accumulation) in the same time that is required for one addition in the Arithmetic and Logic Unit (ALU). In order to overcome these problems, (large delay, and relatively inefficient implementation) a new class of fast FIR filtering algorithms was proposed [l]. These algorithms maintain partially the multiply-accumulate structure of the original inner-product formulation, while reducing the arithmetic complexity. Both characteristics seem to have the potential for deriving efficient implementations on DSPs, even if one restricts to small block processing, (small YO delay) which is suitable in many applications. The main building blocks of these algorithms are short length …